IP-EP200: IP Cyclone II FPGA with Digital I/O (JTAG-configured)

Key features:

• Altera Cyclone II EP2C20 FPGA
• Four models available:
  • IP-EP201: 48 TTL I/O lines
  • IP-EP202: 24 differential RS485 I/O lines
  • IP-EP203: 24 TTL and 12 RS485 I/O lines
  • IP-EP204: 24 LVDS I/O lines
• FPGA programmable via JTAG port or IP bus
• Local static RAM (64K x 16) under FPGA control
• LVTTL external clock connected directly to the FPGA
• Supports 8MHz and 32MHz IP bus
• Programmable PLL-based clock synthesizer
• Example FPGA design code provided as VHDL
  • 8MHz IP bus interface
  • Digital I/O control register
  • others
• Hardware support for DMA and memory space
• 0°C to 70°C (-40°C to 85°C E models)

Datasheet EDK Contents